JPS6069866A - ２進デ−タの符号変換方法 - Google Patents

２進デ−タの符号変換方法

Info

Publication number
JPS6069866A
JPS6069866A JP17857483A JP17857483A JPS6069866A JP S6069866 A JPS6069866 A JP S6069866A JP 17857483 A JP17857483 A JP 17857483A JP 17857483 A JP17857483 A JP 17857483A JP S6069866 A JPS6069866 A JP S6069866A
Authority
JP
Japan
Prior art keywords
signal
data
code
inverted
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17857483A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0534747B2 (en]
Inventor
Noburo Ito
修朗 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP17857483A priority Critical patent/JPS6069866A/ja
Publication of JPS6069866A publication Critical patent/JPS6069866A/ja
Publication of JPH0534747B2 publication Critical patent/JPH0534747B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
JP17857483A 1983-09-26 1983-09-26 ２進デ−タの符号変換方法 Granted JPS6069866A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17857483A JPS6069866A (ja) 1983-09-26 1983-09-26 ２進デ−タの符号変換方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17857483A JPS6069866A (ja) 1983-09-26 1983-09-26 ２進デ−タの符号変換方法

Publications (2)

Publication Number Publication Date
JPS6069866A true JPS6069866A (ja) 1985-04-20
JPH0534747B2 JPH0534747B2 (en]) 1993-05-24

Family

ID=16050851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17857483A Granted JPS6069866A (ja) 1983-09-26 1983-09-26 ２進デ−タの符号変換方法

Country Status (1)

Country Link
JP (1) JPS6069866A (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0932258A4 (en) * 1996-10-13 1999-12-08 Sanyo Electric Co DIGITAL MODULATION METHOD AND CIRCUIT AND DIGITAL DEMODULATION METHOD AND CIRCUIT

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0932258A4 (en) * 1996-10-13 1999-12-08 Sanyo Electric Co DIGITAL MODULATION METHOD AND CIRCUIT AND DIGITAL DEMODULATION METHOD AND CIRCUIT
US6654425B1 (en) 1996-10-13 2003-11-25 Sanyo Electric Co., Ltd. Method and circuit for digital modulation and method and circuit for digital demodulation

Also Published As

Publication number Publication date
JPH0534747B2 (en]) 1993-05-24

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